Freescale Semiconductor /MKM14ZA5 /SIM /CLKDIV1

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Interpret as CLKDIV1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SYSCLKMODE 0 (0000)SYSDIV

SYSDIV=0000, SYSCLKMODE=0

Description

System Clock Divider Register 1

Fields

SYSCLKMODE

System Clock Mode

0 (0): 1:1:1

1 (1): 2:1:1

SYSDIV

System Clock divider

0 (0000): Divide by 1

1 (0001): Divide by 2

2 (0010): Divide by 3

3 (0011): Divide by 4 and so on… If FOPT[0] is 0, the divider is set to div-by-8 after system reset is deasserted (after completion of system initialization sequence)

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